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rev. 1.0 4/12 copyright ? 2012 by silicon laboratories si5330 si5330 1.8/2.5/3.3 v l ow -j itter , l ow -s kew c lock b uffer /l evel t ranslator features applications functional block diagram ? supports single-ended or differential input clock signals ? generates four differential (lvpecl, lvds, hcsl) or eight single-ended (cmos, sstl, hstl) outputs ? provides signal level translation ?? differential to single-ended ?? single-ended to differential ?? differential to differential ?? single-ended to single-ended ? wide frequency range ?? lvpecl, lvds: 5 to 710 mhz ?? hcsl: 5 to 250 mhz ?? sstl, hstl: 5 to 350 mhz ?? cmos: 5 to 200 mhz ? additive jitter: 150 fs rms typ ? output-output skew: 100 ps ? propagation delay: 2.5 ns typ ? single core supply with excellent psrr: 1.8, 2.5, or 3.3 v ? output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 v ? loss of signal (los) indicator allows system clock monitoring ? output enable (oeb) pin allows glitchless control of output clocks ? low power: 10 ma typical core current ? industrial temperature range: ?40 to +85 c ? small size: 24-lead, 4 x 4 mm qfn ? high speed clock distribution ? ethernet switch/router ? sonet / sdh ? pci express 2.0/3.0 ? fibre channel ? msan/dslam/pon ? telecom line cards single-ended or differential single-ended or differential si5330 oeb control los in v dd v ddo0 clk0 v ddo1 clk1 v ddo2 clk2 v ddo3 clk3 ordering information: see page 14. pin assignments in3 in2 rsvd_gnd in1 clk2b clk2a vddo2 vddo1 clk1b clk1a vdd rsvd_gnd vdd rsvd_gnd clk3a clk3b los oeb vddo0 clk0b clk0a vddo3 gnd gnd rsvd_gnd rsvd_gnd 24 23 22 21 20 19 7 8 9 10 11 12 5 4 3 2 1 6 14 15 16 17 18 13
si5330 2 rev. 1.0 1. functional block diagrams based on orderable part number * figure 1. si5330 functional block diagrams *note: see table 11 for detailed ordering information. oeb control los in1 v ddo1 v ddo2 v ddo3 v ddo0 si5330a/b/c in2 clk0a clk0b clk1a clk1b clk2a clk2b clk3a clk3b 1:4 differential to differential buffer in3 1:8 single-ended to single-ended buffer oeb control clk0a los in3 v ddo1 v ddo2 v ddo3 v ddo0 si5330f clk0b clk1a clk1b clk2a clk2b clk3a clk3b in1 in2 1:8 differential to single-ended buffer oeb control clk0a los in1 v ddo1 v ddo2 v ddo3 v ddo0 si5330g/h/j clk0b clk1a clk1b clk2a clk2b clk3a clk3b in2 in3 oeb control los in3 v ddo1 v ddo2 v ddo3 v ddo0 si5330k/l/m clk0a clk0b clk1a clk1b clk2a clk2b clk3a clk3b 1:4 single-ended to differential buffer in1 in2
si5330 rev. 1.0 3 t able of c ontents section page 1. functional block diagrams based on orderable part number* . . . . . . . . . . . . . . . . . . .2 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. vdd and vddo suppl ies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. loss of signal indicator (los) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. output enable (oeb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4. input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5. output driver formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6. input and output terminati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. ordering the si5330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. orderable part numbers and device functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7. package outline: 24-lead qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.1. si5330 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2. top marking explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
si5330 4 rev. 1.0 2. electrical specifications table 1. recommended operating conditions (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit ambient temperature t a ?40 25 85 c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.71 1.8 1.98 v output buffer supply voltage v ddon 1.4 ? 3.63 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. table 2. dc characteristics (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit core supply current i dd 50 mhz refclk ? 10 ? ma output buffer supply current i ddox lvpecl, 710 mhz ? ? 30 ma lvds, 710 mhz ? ? 8 ma hcsl, 250 mhz 2 pf load capacitance ??20 ma sstl, 350 mhz ? ? 19 ma cmos, 50 mhz 15 pf load capacitance ??28 ma cmos, 200 mhz 2 pf load capacitance ??28 ma hstl, 350 mhz ? ? 19 ma
si5330 rev. 1.0 5 table 3. performance characteristics (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit clkin loss of signal assert time t los ?2.6 5 s clkin loss of signal de-assert time t los_b after initial start-up time has expired 0.01 0.2 1 s input-to-output propagation delay t prop ?2.54.0 ns output-output skew t dskew outputs at same signal format ??100 ps por to output clock valid t start start-up time for output clocks ?? 2 ms table 4. input and output clock characteristics (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units input clock (ac coupled differential input clocks on pin in1/2) frequency f in 5 ? 710 mhz differential voltage swing v pp 710 mhz input 0.4 ? 2.4 v pp rise/fall time t r /t f 20%?80% ? ? 1.0 ns duty cycle dc < 1 ns tr/tf 40 50 60 % input impedance r in 10 ? ? k ? input capacitance c in ?3 . 5?p f input clock (dc-coupled single-ended input clock on pin in3) frequency f in cmos 5 ? 200 mhz hstl, sstl 5 ? 350 mhz input voltage v i ?0.1 ? vdd v input voltage swing (cmos standard) 200mhz, tr/tf=1.3ns 0.8 ? ? vpp rise/fall time t r /t f 20%?80% ? ? 4 ns duty cycle dc < 2 ns tr/tf 40 50 60 % input capacitance c in ?2?p f output clocks (differential) frequency f out lvpecl, lvds 5 ? 710 mhz hcsl 5 ? 250 mhz
si5330 6 rev. 1.0 lvpecl output voltage v oc common mode ? v ddo ? 1.45 v ?v v sepp peak-to-peak single- ended swing 0.55 0.8 0.96 v pp lvds output voltage (2.5/3.3 v) v oc common mode 1.125 1.2 1.275 v v sepp peak-to-peak single- ended swing 0.25 0.35 0.45 v pp lvds output voltage (1.8 v) v oc common mode 0.8 0.875 0.95 v v sepp peak-to-peak single- ended swing 0.25 0.35 0.45 v pp hcsl output voltage v oc common mode 0.35 0.375 0.400 v v sepp peak-to-peak single- ended swing 0.575 0.725 0.85 v pp rise/fall time t r /t f 20%?80% ? ? 450 ps duty cycle* dc ckn < 350 mhz 45 ? 55 % 350 mhz < clkn < 710 mhz 40 ? 60 % output clocks (single-ended) frequency f out cmos 5 ? 200 mhz sstl, hstl 5 ? 350 mhz cmos 20%-80% rise/fall time t r /t f 2 pf load ? 0.45 0.85 ns cmos 20%-80% rise/fall time t r /t f 15 pf load ? ? 1.7 ns cmos output resistance ?5 0? ? sstl output resistance ?5 0? ? hstl output resistance ?5 0? ? cmos output voltage v oh 4 ma load vddo?0.3 ? v v ol 4 ma load ? 0.3 v sstl output voltage v oh sstl-3 vddox = 2.97 to 3.63 v 0.45xvddo+0.41 ? ? v v ol ?? 0.45xvddo ?0.41 v v oh sstl-2 vddox = 2.25 to 2.75 v 0.5xvddo+0.41 ? ? v v ol ?? 0.5xvddo? 0.41 v v oh sstl-18 vddox = 1.71 to 1.98 v 0.5xvddo+0.34 ? v v ol ?? 0.5xvddo? 0.34 v table 4. input and output clock characteristics (continued) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units
si5330 rev. 1.0 7 hstl output voltage v oh vddo = 1.4 to 1.6 v 0.5xvddo +0.3 ? ? v v ol ?? 0.5xvddo ?0.3 v duty cycle * dc 45 ? 55 % *note: input clock has a 50% duty cycle. table 5. oeb input specifications parameter symbol test condition min typ max unit input voltage low v il ? ? 0.3 x v dd v input voltage high v ih 0.7 x v dd ?? v input resistance r in 20 ? ? k ? table 6. output control pins (los) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol condition min typ max unit output voltage low v ol i sink =3ma 0 ? 0.4 v rise/fall time 20?80% t r /t f c l < 10 pf, pull up ?? 1k ? ? ? 10 ns table 7. jitter specifications (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test c ondition min typ max unit additive phase jitter (12khz?20mhz) t rphase 0.7 v pk-pk differential input clock at 622.08 mhz with 70 ps rise/fall time ? 0.150 ? ps rms additive phase jitter (50khz?80mhz) t rphasewb 0.7 v pk-pk differential input clock at 622.08 mhz with 70 ps rise/fall time ? 0.225 ? ps rms table 8. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 37 c/w thermal resistance junction to case ? jc still air 25 c/w table 4. input and output clock characteristics (continued) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units
si5330 8 rev. 1.0 table 9. absolute maximum ratings 1,2,3,4,5 parameter symbol test condition value unit dc supply voltage v dd ?0.5 to 3.8 v storage temperature range t stg ?55 to 150 c esd tolerance hbm (100 pf, 1.5 k ? ) 2.5 kv esd tolerance cdm 550 v esd tolerance mm 175 v latch-up tolerance jesd78 compliant junction temperature t j 150 c soldering temperature (pb-free profile) 5 t peak 260 c soldering temperature time at t peak (pb-free profile) 5 t p 20?40 sec notes: 1. permanent device damage may occur if the absolute maxi mum ratings are exceeded. functional operation should be restricted to the conditions as specifi ed in the operational sections of this data sheet. exposure to maximum rating conditions for extended periods may affect device reliability. 2. 24-qfn package is rohs compliant. 3. for more packaging information, go to www.silabs.com/support/qualit y/pages/rohsinformation.aspx . 4. moisture sensitivity level is msl3. 5. recommended card reflow profile is per the jedec/ip c j-std-020 specification for small body components.
si5330 rev. 1.0 9 3. functional description the si5330 is a low-jitte r, low-skew fanout buffer optimized for high-performance pcb clock distribution applications. the device prod uces four differential or eight single-ended, low-jitter output clocks from a single input clock. the input can accept either a single-ended or a differential clock allowing the device to function as a clock level translator. 3.1. v dd and v ddo supplies the core v dd and output v ddo supplies have separate and independent supply pins allowing the core supply to operate at a different voltage than the i/o voltage levels. the v dd supply powers the core functions of the device, which operates from 1.8, 2.5, or 3.3 v. using a lower supply voltage helps minimize the device?s power consumption. the v ddo supply pins are used to set the output signal levels and must be set at a voltage level compatible with the output signal format. 3.2. loss of signal indicator (los) the input is monitored for a valid clock signal using an los circuit that monitors input clock edges and declares an los condition when signal edges are not detected over a 1 to 5 s observation period. the los pin is asserted ?low? when acti vity on the input clock pin is present. a ?high? level on the los pin indicates a loss of signal (los). the los pin must be pulled to vdd as shown in figure 2. figure 2. los indicator with external pull-up 3.3. output enable (oeb) the output enable (oeb) pin allows disabling or enabling of the outputs clo cks (clk0-clk3). the output enable is logically controlled to ensure that no glitches or runt pulses are generated at the output as shown in figure 3. figure 3. oeb glitchless operation all outputs are enabled when the oeb pin is connected to ground or below the v il voltage for this pin. connecting the oeb pin to vdd or above the v ih level will disable the outputs. both v il and v ih are specified in table 5. all outputs are forced to a logic ?low? when disabled. the oeb pin is 3.3 v tolerant. 3.4. input signals the si5330 can accept single-ended and differential input clocks. see ?an408: te rmination options for any- frequency, any-output clock generators and clock buffers?si5338, si5334, si5330? for details on connecting a wide variety of signals to the si5330 inputs. 3.5. output driver formats the si5330 supports single-ended output formats of cmos, sstl, and hstl and differential formats of lvds, lvpecl, and hcsl. it is normally required that the lvds driver be dc-coupled to the 100 : termination at the receiver end. if your application requires an ac- coupled 100 : load, contact the applications team for advice. see an408 for additional information on the terminations for these driver types. 3.6. input and output terminations see an408 for detailed information. 4. ordering the si5330 the si5330 can be ordered to meet the requirements of the most commonly-used input and output signal types, such as cmos, sstl, hstl, lvpecl, lvds, and hscl. see figure 1, ?si5330 functional block diagrams,? on page 2 and table 11, ?order numbers and device functionality,? on page 14 for specific ordering information. si5330 control los in v ddo0 clk0 v ddo1 clk1 v ddo2 clk2 v ddo3 clk3 v dd 1k valid clock no clock 0 1 in clkn oeb enable disable disable enable
si5330 10 rev. 1.0 5. pin descriptions note: center pad must be tied to gnd for normal operation. table 10. si5330 pin descriptions pin # pin name i/o signal type description 1i n 1 im u l t i si5330a/b/c/g/h/j differ ential input devices. these pins are used as the differential clock input. in1 is the positive input; in2 is the negative input. refer to ?an408: termination options for any-frequency, any- output clock generators and clock buffers?si5338, si5334, si5330? for interfacing and termination details. si5330f/k/l/m single-ended input devices. these pins are not used. leave in1 unconnected and in2 connected to ground. 2 in2 i multi 3in3 imulti si5330f/k/l/m single-ended devices. this is the single-ended cloc k input. refer to an408 for interfacing and termination details. si5330a/b/c/g/h/j differ ential input devices. this pin is not used. connect to ground. 4rsvd_gnd ground. must be connected to system ground. 5rsvd_gnd ground. must be connected to system ground. 6rsvd_gnd ground. must be connected to system ground. in3 in2 rsvd_gnd in1 clk2b clk2a vddo2 vddo1 clk1b clk1a vdd rsvd_gnd vdd rsvd_gnd clk3a clk3b los oeb vddo0 clk0b clk0a vddo3 gnd gnd rsvd_gnd rsvd_gnd 24 23 22 21 20 19 7 8 9 10 11 12 5 4 3 2 1 6 14 15 16 17 18 13
si5330 rev. 1.0 11 7 vdd vdd supply core supply voltage. the device operates from a 1. 8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located ve ry close to this pin. 8 los o open drain loss of signal indicator. 0 = clkin present. 1 = loss of signal (los). this pin requires an external ? 1k ?? pull-up resistor. 9 clk3b o multi si5330a/b/c/k/l/m differential output devices. this is the negative side of the differential clk3 output. refer to an408 for interfacing and termination details. leave unconnected when not in use. si5330f/g/h/j single-e nded output devices. this is one of the single-ended clk3 outputs. both clk3a and clk3b single-ended outputs are in phase. refer to an408 for interfacing and termination details. leave unconnected when not is use. 10 clk3a o multi si5330a/b/c/k/l/m differential devices. this is the positive side of the differential clk3 output. refer to an408 for interfacing and termination details. leave unconnected when not in use. si5330f/g/h/j single-ended devices. this is one of the single-ended clk3 outputs. both clk3a and clk3b single-ended outputs are in phase. refer to an408 for interfacing and termination details. leave unconnected when not is use. 11 vddo3 vdd supply output clock supply voltage. supply voltage for clk3a/b. use a 0.1 f bypass cap as close as possible to this pi n. if clk3 is not used, this pin must be tied to v dd (pin 7 and/or pin 24). 12 rsvd_gnd ground. must be connected to system ground. 13 clk2b o multi si5330a/b/c/k/l/m differential output devices. this is the negative side of the differential clk2 output. refer to an408 for interfacing and termination details. leave unconnected when not in use. si5330f/g/h/j single-e nded output devices. this is one of the single-ended clk2 outputs. both clk2a and clk2b single-ended outputs are in phase. refer to an408 for interfacing and termination details. leave unconnected when not is use. table 10. si5330 pin descriptions (continued) pin # pin name i/o signal type description
si5330 12 rev. 1.0 14 clk2a o multi si5330a/b/c/k/l/m differential devices. this is the positive side of the differential clk2 output. refer to an408 for interfacing and termination details. leave unconnected when not in use. si5330f/g/h/j single-ended devices. this is one of the single-ended clk2 outputs. both clk2a and clk2b single-ended outputs are in phase. refer to an408 for interfacing and termination details. leave unconnected when not is use. 15 vddo2 vdd supply output clock supply voltage. supply voltage for clk2a/b. use a 0.1 f bypass cap as close as possible to this pi n. if clk2 is not used, this pin must be tied to v dd (pin 7 and/or pin 24). 16 vddo1 vdd supply output clock supply voltage. supply voltage for clk1a,b. use a 0.1 f bypass cap as close as possible to this pi n. if clk1 is not used, this pin must be tied to v dd (pin 7 and/or pin 24). 17 clk1b o multi si5330a/b/c/k/l/m differential output devices. this is the negative side of the differential clk1 output. refer to an408 for interfacing and termination details. leave unconnected when not in use. si5330f/g/h/j single-e nded output devices. this is one of the single-ended clk1 outputs. both clk1a and clk1b single-ended outputs are in phase. refer to an408 for interfacing and termination details. leave unconnected when not is use. 18 clk1a o multi si5330a/b/c/k/l/m differential devices. this is the positive side of the differential clk1 output. refer to an408 for interfacing and termination details. leave unconnected when not in use. si5330f/g/h/j single-ended devices. this is one of the single-ended clk1 outputs. both clk1a and clk1b single-ended outputs are in phase. refer to an408 for interfacing and termination details. leave unconnected when not is use. 19 oeb i cmos output enable. all outputs are enabled when the oeb pin is connected to ground or below the v il voltage for this pin. connect- ing the oeb pin to v dd or above the v ih level will dis- able the outputs. both v il and v ih are specified in table 5. all outputs are forced to a logic ?low? when dis- abled. this pin is 3.3 v tolerant. 20 vddo0 vdd supply output clock supply voltage. supply voltage for clk0a,b. use a 0.1 f bypass cap as close as possible to this pi n. if clk2 is not used, this pin must be tied to v dd (pin 7 and/or pin 24). table 10. si5330 pin descriptions (continued) pin # pin name i/o signal type description
si5330 rev. 1.0 13 21 clk0b o multi si5330a/b/c/k/l/m differential output devices. this is the negative side of the differential clk0 output. refer to an408 for interfacing and termination details. leave unconnected when not in use. si5330f/g/h/j single-ended output devices. this is one of the single-ended clk0 outputs. both clk0a and clk0b single-ended outputs are in phase. refer to an408 for interfacing and termination details. leave unconnected when not is use. 22 clk0a o multi si5330a/b/c/k/l/m differential devices. this is the positive side of the differential clk0 output. refer to an408 for interfacing and termination details. leave unconnected when not in use. si5330f/g/h/j single-ended devices. this is one of the single-ended clk0 outputs. both clk0a and clk0b single-ended outputs are in phase. refer to an408 for interfacing and termination details. leave unconnected when not is use. 23 rsvd_gnd ground. must be connected to system ground. 24 vdd vdd supply core supply voltage. the device operates from a 1. 8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located ve ry close to this pin. gnd pad gnd gnd supply ground pad. this is main ground connection for this device. it is located at the bottom center of the package. use as many vias as possible to connect this pad to the main ground plane. the device will no t function as specified unless this ground pad is properly connected to ground. table 10. si5330 pin descriptions (continued) pin # pin name i/o signal type description
si5330 14 rev. 1.0 6. orderable part number s and device functionality table 11. order numbers and device functionality part number 1,2 input signal format output signal format number of outputs frequency range lvpecl buffers SI5330A-A00200-GM differential 3.3 v lvpecl 4 5 to 710 mhz si5330a-a00202-gm differential 2.5 v lvpecl 4 5 to 710 mhz lvds buffers si5330b-a00204-gm differential 3.3 v lvds 4 5 to 710 mhz si5330b-a00205-gm differential 2.5 v lvds 4 5 to 710 mhz si5330b-a00206-gm differential 1.8 v lvds 4 5 to 710 mhz hcsl buffers si5330c-a00207-gm differential 3.3 v hcsl 4 5 to 250 mhz si5330c-a00208-gm differential 2.5 v hcsl 4 5 to 250 mhz si5330c-a00209-gm differential 1.8 v hcsl 4 5 to 250 mhz cmos buffers si5330f-a00214-gm single-ended 3.3 v cmos 8 5 to 200 mhz si5330f-a00215-gm single-ended 2.5 v cmos 8 5 to 200 mhz si5330f-a00216-gm single-ended 1.8 v cmos 8 5 to 200 mhz cmos buffers (differential input) si5330g-a00217-gm differential 3.3 v cmos 8 5 to 200 mhz si5330g-a00218-gm differential 2.5 v cmos 8 5 to 200 mhz si5330g-a00219-gm differential 1.8 v cmos 8 5 to 200 mhz sstl buffers (differential input) si5330h-a00220-gm differential 3.3 v sstl 8 5 to 350 mhz si5330h-a00221-gm differential 2.5 v sstl 8 5 to 350 mhz si5330h-a00222-gm differential 1.8 v sstl 8 5 to 350 mhz hstl buffers (differential input) si5330j-a00223-gm differential 1.5 v hstl 8 5 to 350 mhz lvpecl buffers (single-ended input) si5330k-a00224-gm single-ended 3.3 v lvpecl 4 5 to 350 mhz si5330k-a00226-gm single-ended 2.5 v lvpecl 4 5 to 350 mhz notes: 1. custom configurations with mixed output types are also available. pleas e contact the factory for ordering details. 2. add an ?r? to the part number to specify tape and reel shipment media. when specifying non-tape-and-reel shipment media, contact your sales representative for more information.
si5330 rev. 1.0 15 lvds buffers (si ngle-ended input) si5330l-a00228-gm single-ended 3.3 v lvds 4 5 to 350 mhz si5330l-a00229-gm single-ended 2.5 v lvds 4 5 to 350 mhz si5330l-a00230-gm single-ended 1.8 v lvds 4 5 to 350 mhz hcsl buffers (single-ended input) si5330m-a00231-gm single-ended 3.3 v hcsl 4 5 to 250 mhz si5330m-a00232-gm single-ended 2.5 v hcsl 4 5 to 250 mhz si5330m-a00233-gm single-ended 1.8 v hcsl 4 5 to 250 mhz table 11. order numbers and device functionality (continued) part number 1,2 input signal format output signal format number of outputs frequency range notes: 1. custom configurations with mixed output types are also available. pleas e contact the factory for ordering details. 2. add an ?r? to the part number to specify tape and reel shipment media. when specifying non-tape-and-reel shipment media, contact your sales representative for more information.
si5330 16 rev. 1.0 7. package outline: 24-lead qfn figure 4. 24-lead quad flat no-lead (qfn) table 12. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 4.00 bsc. d2 2.35 2.50 2.65 e 0.50 bsc. e 4.00 bsc. e2 2.35 2.50 2.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the je dec/ipc j-std-020 specif ication for small body components. 5. j-std-020 msl rating: msl3. 6. terminal base alloy: cu. 7. terminal plating/grid array material: au/nipd. 8. for more packaging information, go to www.silabs.com/support/quality/ pages/rohsinformation.aspx .
si5330 rev. 1.0 17 8. recommended pcb layout table 13. pcb land pattern dimension min nom max p1 2.50 2.55 2.60 p2 2.50 2.55 2.60 x1 0.20 0.25 0.30 y1 0.75 0.80 0.85 c1 3.90 c2 3.90 e0 . 5 0 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. connect the center ground pad to a ground plane with no less than five vias to a ground plane that is no more than 20 mils below it. via drill size should be no smaller than 10 mils. a longer distance to the ground plane is allowed if more vias are used to keep the inductance from increasing. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil wit h trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 9. a 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ ipc j-std-020c specificatio n for small body components.
si5330 18 rev. 1.0 9. top marking 9.1. si5330 top marking 9.2. top marking explanation mark method: laser line 1 marking: device part number si5330 line 2 marking: x = frequency and configuration code. xxxxx = input and output format configu- ration code. see "6. orderable part numbers and device functionality" on page 14 for more information. xxxxxx line 3 marking: r = product revision (a). ttttt = manufacturing trace code. rttttt line 4 marking: pin 1 indicator. circle with 0.5 mm diameter; left-justified yy = year. ww = work week. characters correspond to the year and work week of package assembly. yyww yyww rttttt xxxxxx si5330
si5330 rev. 1.0 19 d ocument c hange l ist revision 0.1 to revision 0.2 ? clarified documentation to reflect that pin 19 is oeb (oe enable low). ? updated table 4, ?jitter specifications? on page 7. revision 0.2 to revision 0.3 ? major editorial updates to improve clarity. ? updated ?additive jitter? specification table. ? updated ?core supply current? specification in ta b l e 2 . ? removed the low-power lvpecl output options from the ordering table in section 6. ? removed d/e ordering options. revision 0.3 to revision 0.35 ? typo of 150 ps on front page changed to 150 fs. ? updated pcb layout notes. ? added no ac coupling for lvds outputs. ? changed input rise/fall time spec to 2 ns. revision 0.35 to revision 1.0 ? added maximum junction temperature specification to table 9 on page 8. ? added minimum and maximum duty cycle specifications to table 4 on page 5. ? updated table 3, ?performance characteristics,? on page 5. ?? added maximum propagation delay spec (4 ns). ?? added test condition to t los_b in table 3 on page 5. ?? removed reference to frequency in output-output skew. ? updated table 4, ?input and output clock characteristics,? on page 5. ?? input voltage (max) changed ?3.63? to ?vdd? ?? input voltage swing (max) change ?3.63? with ???. ? added table 6, ?output control pins (los),? on page 7. ? added tape and reel ordering information to "6. orderable part numbers and device functionality" on page 14. ? added "9. top marking" on page 18.
si5330 20 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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